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| E2U0033-28-81 Semiconductor MSM6981-01 Semiconductor 32 kbps ADPCM TRANSCODER This version: Aug. 1998 MSM6981-01 Previous version: Nov. 1996 GENERAL DESCRIPTION The MSM6981-01 is for performing high-efficiency compression to code an A/D converted audio-band PCM signal into an ADPCM signal with a transmission rate of 32 kbps, or conversely for converting an ADPCM signal to a PCM signal. With digital-digital conversion in particular, if this device is used as a PCM-ADPCM mutual converter (transcoder) between existing PCMs and CODECs, efficiency can be doubled with respect to conventional transmission lines without loss of call quality. This device may be used in high-speed digital dedicated line multiplexors, digital circuit multiplexors and digital PBX's, or in audio band signal coders/decoders for this kind of equipment. The MSM6981-01 cannot transfer data to and from the MSM6980-03 (MSM6980 family). FEATURES * Provides 9600 bps modem signal (conformed with ITU-T V.29) transmission capability * High quality transmission characteristics equal to or better than ITU-T G.721 (ADPCM specification) for voice signals and tone signals * Provides 24 kbps ADPCM transmission capability for voice signals * Can be interfaced with m-law or A-law PCM CODECs * Can operate as ADPCM encoder or decoder (selection of operation mode) * Asynchronous data input and output * Serial or parallel data interface * Usable clock rate of 32 kbps to 2048 kbps for serial input or output * Selectable 3 bit or 4 bit data conversion * Low power consumption: +5 V, 70 mW (Typ.) * Package: 42-pin plastic DIP (DIP42-P-600-2.54) (Product name : MSM6981-01RS) 1/15 Semiconductor PATH: Prediction filter controlled by Advanced Tchebycheff equation and Hurwitz stability BLOCK DIAGRAM A/m C/D 3BIT MODE SELECT Nonlinear AELinear Adaptive Quantizer Adaptive Inverse Quantizer Adaptive Zero Filter PATH SID SICK S/P CODER BLOCK DECODER BLOCK ISYNC OSYNC IS/P Linear AENonlinear Adaptive Zero Filter P/S SOD SOCK I/O CONT. Adaptive Inverse Quantizer PATH WDT P. I/O PORT VDD GND MCK RST CKOUT CLOCK GENE. -- PD15 to 0 MSM6981-01 2/15 Semiconductor MSM6981-01 PIN CONFIGURATION (TOP VIEW) PD6 1 PD7 2 PD8 3 PD9 4 PD10 5 PD11 6 PD12 7 PD13 8 PD14 9 PD15 10 SID 11 SICK 12 ISYNC 13 MCK 14 PBS 15 RST 16 DATD 17 POWD 18 WDT 19 EXTI 20 GND 21 42-Pin Plastic DIP 42 VDD 41 PD5 40 PD4 39 PD3 38 PD2 37 PD1 36 PD0 35 SOD 34 SOCK 33 BTST 32 OSYNC 31 A/m 30 8IO 29 CNV/TH 28 3BIT 27 SADJ 26 SIGI/O 25 C/D 24 CKRST 23 IS/P 22 CKOUT 3/15 Semiconductor MSM6981-01 PIN DESCRIPTION Pin Symbol Bidirectional bus interface. PD15 is the MSB pin. 1 to 10 36 to 41 PD0 to PD15 Refer to Tables 1 and 2 for the specifications and Figures 1 and 3 for the timings. When RST or OSYNC is a logic "0", all of outputs PD0 to PD15 are "1"s with an impedance of 100 kW or more. A logic "0" means low level input/output voltage and a logic "1" high level input/output voltage. 11 SID Serial data input. The bit length is 4 or 8. Refer to Fig.2. Clock signal input for serial input data. 12 SICK The maximum clock rate is 2048 kbps. The input clock count should be longer than the serial data bit length. Refter to Fig.2. 13 14 15 ISYNC MCK PBS Synchronous pulse signal input. For taking in the serial or parallel data. Main clock input. 20 MHz clock input. Chip test input. Input a logic "0" to this pin. Reset signal input. Input a logic "0" while the main clock (MCK) is input. Provide the timing indicated 16 RST in Fig.6 to make the first output data effective. While a logic "0" is input to RST, PD0 to PD15 output a logic "1" with a high output impedance of 100 kW or more, and SOD is in a high impedance state. 17 18 DATD POWD Chip test output. Chip test output. Chip test output. 19 WDT Also available for the internal observation signal. When the device is operating normally, the signal synchronized with ISYNC is output from WDT. Refter to Fig.5. 20 21 22 EXTI GND CKOUT Chip test input. Normally input a logic "1" to this pin. Ground. 0 V. Chip test output. Normally 1/4 main clock (MCK) frequency is output (5 MHz). Serial/Parallel data input select signal. Logic "1": Serial data input. Logic "0": Parallel data input. Refer to Table 1. 24 CKRST Chip test input. Normally pull this pin to a logic "1". Operating mode select input. 25 C/D Logic "1": Coding mode. Logic "0": Decoding mode. Refer to Table 1. Description 23 IS/P 4/15 Semiconductor MSM6981-01 Pin 26 27 Symbol SIGI/O SADJ Chip test input and output. Normally remain this pin open. Chip test input. Description Normally pull this pin to a logic "0". ADPCM data bit length select signal. Logic "1": 3 bits Logic "0": 4 bits Refer to Table 2. Chip test input. Normally pull this pin to either a logic "1" or "0". Chip test input. Normally pull this pin to a logic "0". PCM coding law select input. Logic "1": A-law Logic "0": m-law Parallel or serial output control. Refer to Fig.3 and Fig.4. Chip test input. Pull this pin to a logic "1". Clock input for serial data output control. The maximum output data rate is 2048 kbps. Refer to Fig.4. Serial data output. The data bit length is 4 or 8. After the determined number of bits has been sent 28 3BIT 29 30 CNV/TH 8IO 31 A/m 32 33 OSYNC BTST 34 SOCK 35 SOD from SOD, SOD is in a high impedance state. The fourth bit is a logic "0" when the bit length is three. Refer to Fig.4. 42 VDD +5 V power supply. 5/15 Semiconductor Input/Output Setting Table Table-1 Operating Mode Coder Decoder Input Bit Length 8 4 (3) P/S P S P S 4 (3) 8 Output Bit Length P/S Note: P, S Note: P, S MSM6981-01 Control Pin C/D IS/P 1 0 0 1 0 1 P: Parallel format S: Serial format Note: Output in serial or Parallel Table to Indicate the Parallel I/O Pins Table-2 Input I/O Coder Decoder 4-bit 3-bit 4-bit MSB PD15 to 12 LSB PD11 to 8 LSB MSB PD7 to 4 MSB PD3 to 0 LSB LSB MSB LSB Coder 3-bit MSB LSB Output Decoder MSB 6/15 Semiconductor MSM6981-01 ABSOLUTE MAXIMUM RATINGS Parameter Power Supply Voltage Input Voltage Power Dissipation Storage Temperature Symbol VDD VIN PD TSTG -- Ta = 25C Condition Rating -0.3 to +7 -0.3 to VDD + 0.3 1 -65 to +150 Unit V W C RECOMMENDED OPERATING CONDITIONS Parameter Operating Temperature Power Supply Voltage Master Clock Frequency Symbol Ta VDD FC Condition -- -- -- Min. 0 4.75 19.998 Typ. 25 5 20 Max. 70 5.25 25 Unit C V MHz ELECTRICAL CHARACTERISTICS DC Characteristics (In range of Recommended Operating Condition) Parameter Stand-by Power Supply Current Operating Power Supply Current Input Low Voltage Input High Voltage Output Low Voltage Outpu High Voltage Input Leakage Current Input Capacitance Output Load Capacitance Symbol IDD1 IDD2 VIL VIH1 VIH2 VOL1 VOL2 VOH II CI CL Condition Master clock is not input FC = 20 MHz -- MCK, SICK, SOCK Other input pins SOD, IOL = 6.0 mA Other output pins, IOL = 1.6 mA IOH = 40 mA VIN = VDD, GND -- -- Min. -- -- 0 2.4 2.0 0 0 4.2 -10 -- -- Typ. 1.0 14 -- -- -- -- -- -- -- -- -- Max. 2.0 20 0.8 VDD VDD 0.4 0.4 VDD +10 10 100 Unit mA mA V V V V mA pF pF 7/15 Semiconductor MSM6981-01 TIMING DIAGRAM Parallel Data Input 125 ms 300 ns Min. ISYNC PD15 to 0 Input Data 0 s Min. 400 ns Min. Figure 1 Serial Data Input 125 ms T or more ISYNC T SICK SID MSB LSB High-Z 50 ns Min. 0 s 50 ns Min. Min. T : 1/32 kHz to 2048 kHz Figure 2 8/15 Semiconductor Parallel Data Output 125 ms 300 ns Min. MSM6981-01 OSYNC 16 ms Max. PD15 to 0 Output Data 100 ns Max. 100 ns Max. Figure 3 Serial Data Output 125 ms T or more OSYNC 50 ns Min. SOCK 50 ns Min. SOD MSB T LSB High-Z 100 ns Max. 100 ns Max. Figure 4 9/15 Semiconductor WDT (1) Parallel data input MSM6981-01 ISYNC WDT 200 ns Typ. 10 ms to 20 ms 800 ns 400 ns Typ. Typ. (2) Serial data input during coding function ISYNC SICK 1 2 8 WDT 10 ms to 20 ms 200 ns Typ. 800 ns Typ. 400 ns Typ. (3) Serial data input during decoding function ISYNC SICK 1 2 4 WDT 10 ms to 20 ms 200 ns Typ. 800 ns Typ. 400 ns Typ. Figure 5 10/15 Semiconductor RST MSM6981-01 RST 1 ms Min. ISYNC 30 ms Min. Figure 6 11/15 Semiconductor APPLICATION CIRCUIT 1.544 Mbps BUS ADPCM CODER ADPCM DECODER AIN CH1 AOUT PCM CODEC AIN CH2 AOUT AIN AOUT PCMOUT SYNC CLOCK PCMIN SID ISYNC SICK SOD OSYNC SICK SOD OSYNC MCK SID ISYNC MCK AIN CH48 AOUT AIN AOUT PCMOUT SYNC CLOCK PCMIN SID ISYNC SICK SOD OSYNC SICK 20 MHz SOD OSYNC MCK SID ISYNC MCK 1.544 MHz SYN P-A 1.544M SYN A-A MSM6981-01 12/15 Semiconductor VSS VDD VDD MSM6932 VSS TMC AIN AG AOUT VREF VDD PCMOUT XCLOCK XSYNC DG BS RSYNC RCLOCK PCMIN 2 kW AIN AOUT PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 SID SICK ISYNC MCK PBS RST VDD PD5 PD4 PD3 PD2 PD1 PD0 SOD SOCK OSYNC A/m 8IO CNV/TH 3BIT SADJ SIGI/O C/D IS/P CKOUT CKRST BTST ADPCM OUT MSM6981-01 DATD POWD WDT EXTI GND VDD 10 kW ADPCM IN 1.544 MHz SYNP-A SYNA-A 20 MHz PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 SID SICK ISYNC MCK PBS RST VDD PD5 PD4 PD3 PD2 PD1 PD0 SOD SOCK OSYNC A/m 8IO CNV/TH 3BIT SADJ SIGI/O C/D IS/P CKOUT CKRST BTST MSM6981-01 MSM6981-01 DATD POWD WDT EXTI 13/15 GND Semiconductor MSM6981-01 RECOMMENDATIONS FOR ACTUAL DESIGN Countermeasures for malfunctions caused by instantaneous power supply failures The MSM6981-01 is a digital signal processor (DSP) operated by a built-in program ROM. If the sequence program of device operation runs away, or the stored data in internal memory or in registers is destroyed due to instantaneous power supply failure, the device output becomes abnormal and cannot be recovered automatically unless the external reset signal (RST) is applied. The duration of the instantaneous power supply failure or power voltage drop, and the voltage drop level, which cause malfunctions are specified according to the impedance of the power supply circuit including additional capacitances and inductances, and the pulse waveform at the time of instantaneous power failure. Experimentally, when the duration is about 1 ms or less and the voltage drop level is about 2 V, device malfunctions may occur. To prevent malfunctions due to instantaneous power supply failures, the following actions are recommended. (1) A capacitor (20 mF to 50 mF) and inductance (100 mH to 500 mH) should be inserted closest to the power supply pin of the printed circuit board. (2) A capacitor (0.1 mF to 1.0 mF) should be inserted between the power supply pin and ground pin of the MSM6981-01. (3) A power supply reset signal generation IC should be used. (See the figure below) (4) A WDT monitor circuit should be used. VDD (+5 V) 1 2.2 kW 10 kW MSM6981-01 PST520D 3 RST 0.01 mF Reset SW WDT 2 WDT Monitor Circuit 14/15 Semiconductor MSM6981-01 PACKAGE DIMENSIONS (Unit : mm) DIP42-P-600-2.54 Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 6.20 TYP. 15/15 |
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